1. Field of the Invention
This present invention is generally directed to the field of integrated circuits and semiconductor processing, and, more particularly, to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Complementary metal oxide (CMOS) technology is widely used in various integrated circuit products, such as logic circuits, memory circuits, application-specific integrated circuits, etc., due to various performance characteristics associated with CMOS devices, e.g., lower power consumption. In general, CMOS integrated circuits are comprised of P-channel (PMOS) and N-channel (NMOS) transistors which are formed on the same semiconducting substrate. As a result of such structures, parasitic bipolar transistors (of both the PNP type and the NPN type) are formed in the CMOS integrated circuit. For example, a PNP parasitic transistor is formed where an N-type substrate, which serves as its base, is formed within a P-well, which serves as its collector. The source or drain of a PMOS transistor serves as the emitter of the parasitic PNP transistor. At the same time, an NPN parasitic transistor is possible where the P-well, which serves as the base, is formed within the N-type substrate, which serves as the collector. The source or drain of the NMOS transistor serves as the emitter for the NPN parasitic transistor.
When such a CMOS structure forms an output circuit of an integrated circuit device, a ground voltage (VSS) and a power supply voltage (VCC) are typically supplied to the sources of the NMOS and PMOS transistors, respectively. The drains of the NMOS and PMOS transistors are used for an output terminal of the output circuit. If the output terminal accidentally receives a triggering voltage which is generally higher than the power supply voltage (VCC) or lower than the ground voltage (VSS), the parasitic transistors begin to conduct since the junctions between the base and emitter are forward biased. Once both parasitic transistors become conducting, a current continues to flow in a direction from the power supply voltage (VCC) to the ground voltage (VSS) without any further triggering voltage to the output terminal. This situation is known in the industry as “latch-up.” When latch-up occurs, the CMOS circuits are often permanently damaged by the resulting high currents.
In modern CMOS integrated circuits, the most likely source for the undesirable triggering voltage that may cause latch-up are the pad drivers, where large voltage transients and large currents are present. FIG. 1A is a schematic depiction of various I/O (input/output) voltage supply regions that may be found on a modern integrated circuit 10 employing CMOS technology. As shown therein, the integrated circuit 10 is generally comprised of a core region 12 wherein the various circuits, comprised of PMOS and NMOS transistors, may be formed. In general, there are four types of power rings depicted in FIG. 1A—VDD, GND, VDDIO and GNDIO. Both VDD (14) and GND (16) are connected to the core logic power supply. VDDIO and GNDIO are the supply voltages to the I/O buffers, which drive heavy loads. In the particular embodiment depicted in FIG. 1A, three cuts 18A, 18B, 18C are made in the VDDIO and GNDIO rings to thereby define three separate power supply structures or power domains 20A (VDDIO1), 20B (VDDIO2) and 20C (VDDIO3). Separation of the power supply structures enables chip designers to isolate the various power domains and/or to use different voltage levels for different input/output buffers. As will be understood by those skilled in the art, the depiction of three voltage domains in FIG. 1A is by way of example only, as there may be more or fewer voltage domains on the integrated circuit device, and the magnitudes of the voltages of the various power domains may vary depending upon the particular integrated circuit.
Generally, in an effort to avoid or reduce the possibility of latch-up, a doped region or guard band 13 is formed in the substrate 17 under each of the various power supply structures, e.g., VDDIO1, VDDIO2 and VDDIO3. FIGS. 1B and 1C are, respectively, a plan view and a cross-sectional view of an illustrative power supply structure 10, e.g., VDDIO3, and a simplified version of such a doped region or guard band 13. The illustrative guard band 13 is depicted in FIGS. 1B and 1C is a relatively deep N-well doped region that is formed by implanting the appropriate dopant atoms into the substrate 17. A contact 15 is provided to the guard band 13 so that a voltage may be applied to the guard band 13. FIG. 1D is a cross-sectional view of a guard band 13 comprised of multiple doped regions formed in the substrate 17. More specifically, in the illustrative example depicted in FIG. 1D, the guard band 13 is comprised of, in one embodiment, an N+ active region 13A, an N-well 13B and a deep buried N-well 13C. A layer of insulating material 10A is positioned between the voltage supply structure 10 and the substrate 17. Unfortunately, using such prior art structures, the areas defined by each of the cuts 18A-C in the voltage supply structures still define possible paths for triggering currents and voltages that may enter the core region 12 and cause the latch-up phenomenon to occur.
The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.